A lookup circuit for translating received addresses into destination addresses. The lookup circuit comprises M pipelined memory circuits for storing a trie table for translating a first received address into a first destination address. The M memory circuits are pipelined such that a first portion of the first received address accesses an address table in a first memory circuit. An output of the first memory circuit comprises a first address pointer that indexes a start of an address table in a second memory circuit. The first address pointer and a second portion of the first received address access a particular entry in the address table in the second memory circuit. An output of the second memory circuit comprises a second address pointer that indexes a start of an address table in the third memory circuit, and so forth.