A resistive memory cell that includes a metal-polymer bi-layer proximate a CMOS gate. The memory cell has a substrate having a source contact connected to a source line and a drain contact connected to a drain line, a CMOS gate proximate the substrate electrically connecting the source contact and the drain contact, the bi-layer adjacent the CMOS gate, the bi-layer comprising a thin metal layer and a polymer layer, and a word line connected to the bi-layer.