A display system includes a display panel, a timing controller, a plurality of source drivers and an EDDS interface. The control signals, the clock signals and the setting signals generated by the timing controller are embedded as protocols into the data signals. The embedded signals are then transmitted from the timing controller to each source driver via a corresponding pair of differential data lines of the EDDS interface. The decoders of the source drivers can then decode the embedded signals for generating corresponding driving signals for the display panel.