An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.