Disclosed are a metal line of a semiconductor device and a method of manufacturing the same. In one embodiment, the metal line includes a first interlayer dielectric layer pattern formed on a lower interconnection structure and having a via hole that exposes a lower interconnection of the lower interconnection structure, a first barrier pattern selectively covering a sidewall of the via hole and the lower interconnection, a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench that exposes the via hole, a second barrier pattern covering an inner wall of the trench and the first barrier pattern, a seed pattern formed on the second barrier pattern, and a copper line formed on the seed pattern.