A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a set of entries that correspond to pages of address space. Each entry provides a set of task memory attributes (TMA) (412a-n) for the associated page of address space. Task memory attributes are defined by a task control block associated with a currently executing task. For each memory transfer request, the TLB accesses an entry corresponding to the request address and provides a translated physical memory address and a task memory attribute value associated with that requested address space page. Functional circuitry (470) performs pre/post-processing on data that is being transferred between a processor and the memory in accordance with the task memory attribute value provided by the TLB with each memory transfer request. Thus, data accessed at the same address by different tasks on a same processor or on different processors can be pre-processed or post-processed in a manner defined by a task control block. Such pre/post-processing may include compression/decompression, encryption/decryption, or formatting, for example.