Systems, method, and computer program products for utilizing a spare lane for additional checkbits. Systems include computer, storage or communications systems with bitlanes for transferring error correcting code (ECC) words in packets over a bus in multiple cycles, a spare bitlane available to the bus, a spared mode and an initial mode. The spared mode is executed when the spare bitlane has been deployed as a replacement bitlane for carrying data for one of the other bitlanes. The initial mode is executed when the spare bitlane has not been deployed as a replacement bitlane. The initial mode includes utilizing the spare bitlane for carrying one or more additional ECC checkbits. The initial mode provides at least one of a more robust error detecting function for the bus than the spared mode and a more robust error correcting function for the bus than the spared mode.