A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

 
Web www.patentalert.com

< Stacked ball grid array package module utilizing one or more interposer layers

< Semiconductor device with a line and method of fabrication thereof

> Semiconductor device

> Methods and structures for interconnect passivation

~ 00604