Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.

 
Web www.patentalert.com

< Method for managing volume groups considering storage tiers

< Translated memory protection apparatus for an advanced microprocessor

> Descriptor-based memory management unit and method for memory management

> Apparatus and method for controlling memory interface

~ 00606