A method and apparatus for accelerating processing of a structured
document. A hardware XML accelerator includes one or more processors
(e.g., CMT processors), one or more hardware XML parser units, one or
more cryptographic units and various interfaces (e.g., to memory, a
network, a communication bus). An XML document may be processed in its
entirety or may be parsed in segments (e.g., as it is received). A parser
unit parses a document or segment character by character, validates
characters, assembles tokens from the document, extracts data, generates
token headers (to describe tokens and data) and forwards the token
headers and data for consumption by an application. A cryptographic unit
may enforce web security, XML security or some other security scheme, by
providing encryption/decryption functionality, computing digital
signatures, etc. Software processing, bus utilization and latencies
(e.g., memory, bus) are greatly reduced, thereby providing significantly
improved XML processing and security processing throughput.