A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming "cells" or "packets" stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N.times.N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N.times.N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N.times.N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.