A command decoding system includes a main processor, an instruction memory, a memory controller, and a device controller. The main processor provides a command, and the instruction memory stores an instruction block corresponding to the command. The instruction block includes micro-commands for executing the command. The memory controller controls an access to the instruction memory, and the device controller receives the command, and sequentially fetches the micro-commands included in the instruction block corresponding to the command through the memory controller to execute the fetched micro-commands.