A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.

 
Web www.patentalert.com

< Method and system for centrally exchanging terminal information over a meshed network

< Buffer management method and system with two thresholds

> Serial communications protocol

> Contactless technique for evaluating a fabrication of a wafer

~ 00612