A cache memory device includes a memory section configured to store image data of a frame with a predetermined size as one cache block, and an address conversion section configured to convert a memory address of the image data such that a plurality of different indices are assigned in units of the predetermined size in horizontal direction in the frame so as to generate address data, wherein the image data is output from the memory section as output data by specifying a tag, an index, and a block address based on the address data generated by the address conversion section through conversion.