A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engine for performing bulk transfer of information from the at least one memory location on the network device to the external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second engine for performing bulk transfer of information from the external CPU memory location to at least one memory location on the switching chip, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the switching chip. The second engine uses a bit received from a CPU to determine how entries will be added in the at least one memory location on the switching chip.