A shift register circuit includes a plurality of cascade-connected signal holding circuits each of the signal holding circuits includes an input control circuit to which an input signal is applied, and which fetches and holds the input signal, an output control circuit to which a first control clock signal is applied, and which outputs an output signal corresponding to timings of the held input signal and the first control clock signal, and a reset control circuit to which a reset signal is applied, and which initializes a signal level of the input signal held in the input control circuit. A timing at which the output signal is terminated is set to be ahead of an application start timing of the reset signal.