A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 .mu.m in length and running along a Si<100> direction.

 
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< MOS transistor and manufacturing method thereof

< CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode

> Thermal management substrates

> MOS devices with continuous contact etch stop layer

~ 00615