A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is .alpha., a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is .beta., a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is .gamma., and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is .eta.. .alpha. is substantially different from .beta.. A total capacitance of a feedback capacitor pair is substantially equal to (.alpha.-.beta.-.gamma.+.eta.)(N/2), where N is a positive number.