Enhanced polar modulator for transmitter. Within a phase locked loop
(PLL), a two point modulation topology is employed in which phase
information passes through a limiter (e.g., a +90.degree. or +re/2) in
which the phase information dynamic range is divide by a factor (e.g., by
2) and a maximum frequency deviation is also divided by a factor (e.g.,
by 2). Then, a double balanced up-converter mixer/modulator is
implemented to perform gain adjustment (e.g., magnitude and/or amplitude
adjustment) and phase changes of 0.degree. and +180.degree. or 0 and +re
(e.g., negative gains values may be employed). Phase adjustment in such
an architecture is split and provided to both the PLL and to the
mixer/modulator of such a polar modulator within a transmitter module
such as may be implemented within a communication device (e.g., which may
be a wireless communication device). This architecture that includes a
PLL with a double balanced up-converter mixer/modulator suppresses even
harmonics.