A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.