An interface for controlling the transmission of data between integrated circuit (IC) chips. The interface comprises a data bus for transmitting data from a first integrated circuit chip to a second integrated circuit chip, and a control bus for transmitting control signals between the first and second integrated circuits. The first IC has a memory for receiving data for transmission to the second IC, and the second IC has a scheduler and a data output port, the scheduler being arranged to control the transfer of data from the memory of the first IC to the data output port of the second IC via the data bus. The interface is capable of stopping and reinitiating data transmission on detection of errors in transmitted data, and the interface may include a code transfer bus for transferring error detection code separately from associated data.