An apparatus and method for reducing the power consumption of a multi-cache microprocessor dynamically predicts the misses of an i.sup.th -level (L.sub.i) cache. This method predicts the misses in L.sub.i and accesses the i+1 level cache (L.sub.i+1) concurrently with L.sub.i only if a miss is predicted. If a hit is predicted, L.sub.i+1 is accessed only if the prediction is incorrect. The prediction is based on the fact that misses occur in bursts which correspond to changes of the working set. A circuit implementing this technique occupies a very small area and its delay is not in the critical path of the microprocessor. The prediction is applied to reduce the number of unnecessary accesses to L.sub.i+1, which translates to a reduction in power consumption in the L.sub.i+1 cache.