The specification describes silicon MOS devices with gate dielectrics having the composition Ta.sub.1-x Al.sub.x O.sub.y, where x is 0.03-0.7 and y is 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, where x is 0.05-0.15, and y is 1.5-3, and Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO.sub.2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO.sub.2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.

Les spécifications décrivent des dispositifs de MOS de silicium avec des diélectriques de porte ayant la composition Ta.sub.1-x Al.sub.x O.sub.y, où x est 0.03-0.7 et y est 1.5-3, Ta.sub.1-x Si.sub.x O.sub.y, où x est 0.05-0.15, et y est 1.5-3, et Ta.sub.1-x-z Al.sub.x Si.sub.z O.sub.y, où 0.7 x+z 0.05, z