The timing analysis for semiconductor integrated circuits is mainly made in accordance with the following procedure. First, maximum capacitance and minimum capacitance are determined for each of nodes on a circuit (first step). Static timing analysis is made using the maximum capacitance and the minimum capacitance to determine the timing of paths comprised of one or more of the nodes. The paths are classified into conformable paths in which the timing satisfies a predetermined constraint, nonconformable paths in which the timing does not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths (second step). Dynamic timing analysis is made of the undecided paths to classify them in either the conformable paths or the nonconformable paths (third step).