An RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation parses through annotation data from the back annotation file for the ASIC layout and generates RTL delays for each wire and register in the ASIC layout. The RTL annotator then applies the generated RTL delays to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.