A matched set of integrated circuit chips (74, 78) and a method for
assembling such integrated circuit chips (74, 78) into a matched set are
disclosed. A first semiconductor wafer (62) having a plurality of
integrated circuit chips (74) of a first type and a second semiconductor
wafer (64) having a plurality of integrated circuit chips (78) of a second
type are electrically and mechanically coupled to a pair of interposers
(52, 53) to form a pair of wafer-interposer assemblies (50, 51). The
integrated circuit chips (74, 78) of the first and second wafers (62, 64)
are then tested together. The wafer-interposer assemblies (52, 53) are
then diced into a plurality of chip assemblies having chips (74) of the
first type and a plurality of chip assemblies having chips (78) of the
second type. Based upon the testing, at least one of the chip assemblies
having chips (74) of the first type and at least one of the chip
assemblies having chips (78) of the second type are selected for inclusion
in the matched set.