A method of verifying the layout of an integrated circuit device is provided. In a method of verifying the layout of an integrated circuit device having a memory block, a dummy circuit for receiving and outputting signals which are applied to the input and output ports included in the memory block, is inserted into the memory block. Then, the integrated circuit device is placed and routed using a computer. Next, a circuit-to-layout verification is performed with respect to the integrated circuit device, using a computer. Thus, the time for layout data verification with respect to the integrated circuit device is shortened and the verification made more accurate.