The present invention uses a novel cache memory allowing a high texture calculation rate while using a low cost single bank DRAM hardware. In accordance with this invention, pixels are processed in a cluster, for example by processing pixels within a region as a cluster of pixels, with the regions of pixels arranged in a fixed gridwork across the area of the display with fixed, unchanging boundaries. All polygon-pixels occurrences within a region are processed together in one operation. Texture processing for all polygon-pixels within a region are broken down in to a set of information gathering operations for all polygon-pixels within the region, followed by a high speed fetching of all needed texels to process the entire region. Following this, high speed interpolation operations are preformed via use a specially arranged on chip RAM and a hardware pipeline calculation.