A secure write blocking circuit and method of operation thereof. The secure
write blocking circuit includes enable and disable block input terminals
coupled to a blocking circuit. The blocking circuit, such as a set/reset
latch in a preferred embodiment, generates a block signal to prevent write
access to a nonvolatile memory device, such as flash memory, in response
to signals provided to the enable and disable input terminals. The secure
write blocking circuit also includes an interrupt generator, coupled to
the disable block input terminal, that generates an interrupt signal in
response to a signal at the disable input terminal. In a related
embodiment the secure write blocking circuit also includes a logic
circuit, coupled to the blocking circuit, that receives the block signal
and a write enable signal and in response thereto generates a control
signal to a write enable input of the nonvolatile memory device.
