The present invention provides Performance groups based Simulated Annealing
(PGSA) for VLSI circuit placement. This method reduces the computation
time required for VLSI circuit placement using Simulated Annealing by
reducing the size of the placement problem by forming Performance groups
while maintaining a high quality of the final placement solution.
Performance groups are formed by picking circuits connected by a net and
counting their local-net-count. These circuits are then grouped based on
certain pre-determined conditions and placed suitably using simulated
annealing based placement approach.
