A semiconductor device having a memory cell including first and second load
transistors, first and second driver transistors, and first and second
transfer transistors. The semiconductor device includes first and second
gate--gate electrode layers, first and second drain--drain wiring layers,
and first and second drain-gate wiring layers. The first drain-gate wiring
layer and the second drain-gate wiring layer are located in different
layers. The first drain-gate wiring layer is located below the first
drain--drain wiring layer, and the second drain-gate wiring layer is
located in above the first drain--drain wiring layer. This structure
provides a semiconductor device that has reduced cell area. The invention
also provides a memory system and electronic apparatus that include the
above semiconductor device.
