A sensing circuit for determining the logic state of each memory cell in a
resistive memory array, wherein each memory cell in the resistive memory
array has current control isolation and the logic state of each memory
cell can be determined relative to a reference cell having a pre-selected
logic state. The sensing circuit comprises a memory cell sensing circuit
to determine a bias voltage of a memory cell, a reference cell sensing
circuit to determine a bias voltage of a reference cell, an isolation
circuit to apply an isolation voltage to turn off a current control
element associated with each unselected memory cell, an adjusting circuit
to make the bias voltage on the memory cell approximately equal to the
bias voltage on the reference cell, and a state determining circuit for
determining the logic state of the memory cell.
