A clock switchover circuit includes a NAND circuit supplied with an output
of a first inverter circuit, and a first flip-flop (DFF) supplied with an
output of the NAND circuit. Further, the circuit includes a NOR circuit,
and a second DFF supplied with an output of the NOR circuit. A second
inverter circuit is supplied with an output of the first DFF. A clock
signal selection section is supplied with outputs of the second DFF and
the second inverter circuit. A third inverter circuit is supplied with an
output of the clock signal selection section and produces a clock signal.
