A process is shown for determining crossover current in a circuit design.
One or more static CMOS gates are identified within the circuit design.
One or more widths of at least one of a P-stack and N-stack associated
with the CMOS gates are then determined. A voltage slope at the input of,
and a capacitive load at the output of, one or more of the nodes are also
determined. Crossover current, per static CMOS gate, is estimated based on
the widths, the voltage slope and capacitive load. An overall crossover
current is determined by summing individual gate-level crossover currents.
The circuit design may be optimized for power consumption, for example, by
modifying design elements of the circuit design while monitoring overall
crossover current.
