A semiconductor memory device includes a memory cell block composed of a memory
cell unit having memory cells each containing a ferroelectric capacitor, and a
test memory cell unit having test memory cells. The layout pattern of the test
memory cells is identical to the layout pattern of the memory cells. The test memory
cell unit is arranged close to a memory cell of a plurality of memory cells which
is at a position where the ferroelectric capacitor is susceptible to degradation.
The memory cell unit and test memory cell unit are subjected to a first cycling
test consisting of N1 cycles. Then, the test memory cell unit is subjected
to a second cycling test consisting of N2 cycles. The sum (N1+N2)
of the number of cycles in the first and second cycling tests equals an assurance
number of cycles T, where N1N2.
