A semiconductor device (10) has a highly doped layer (26) having
a first conductivity type uniformly implanted into the semiconductor substrate
(20). An oxide-nitride-oxide structure (36, 38, 40) is formed over
the semiconductor substrate (20). A halo region (46) having the first
conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide
structure and extends under the oxide-nitride-oxide structure a predetermined distance
from an edge of the oxide-nitride-oxide structure. A source (52) and drain
(54) having a second conductivity type are implanted into the substrate
(20). The resulting non-volatile memory cell provides a low natural threshold
voltage to minimize threshold voltage drift during a read cycle. In addition, the
use of the halo region (46) on the drain side allows a higher programming
speed, and the highly doped layer (26) allows the use of a short channel device.
