A ferroelectric memory device includes a simple matrix type memory cell array.
Provided that the maximum absolute value of a voltage applied between a first signal
electrode and a second signal electrode is Vs, polarization P of a ferroelectric
capacitor formed of the first electrode, the second electrode, and ferroelectric
layer is within the range of 0.1P(+Vs)P(-1/3Vs) when the applied voltage
is changed from +Vs to -1/3Vs, and 0.1P(-Vs)P(+1/3Vs) when the applied voltage
is changed from -Vs to +1/3Vs.
