Structures that provide decoupling capacitance to packaged IC devices
with reduced capacitor and via parasitic inductance. A capacitive interposer structure
is physically interposed between the packaged IC and the PCB, thus eliminating
the leads and vias that traverse the PCB in known structures. A capacitive interposer
is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer
has an array of lands on an upper surface, to which the packaged IC is coupled,
and an array of terminals on a lower surface, which are coupled to the PCB. Electrically
conductive vias interconnect each land with an associated terminal on the opposite
surface of the interposer. Within the interposer, layers of a conductive material
alternate with layers of a dielectric material, thus forming parallel plate capacitors
between adjacent dielectric layers. Each conductive layer is either electrically
coupled to, or is electrically isolated from, each via.
