A method for forming shallow trench isolation (STI) for semiconductor devices.
A first hard mask is deposited over a semiconductor wafer, and a second hard mask
is deposited over the first hard mask. The semiconductor wafer includes a first
etching zone and at least a second etching zone disposed beneath the first etching
zone. The etch process for the first etching zone and the etch process for the
at least one second etching zone are selected such that smooth sidewall surface
structures are formed within the semiconductor device. The etch processes for each
subsequent etching zone may alternate between non-selective and selective etch
processes to preserve at least the first hard mask material.
