Structures and methods for programmable logic arrays are provided. In
one embodiment, the programmable logic array includes a first logic plane and a
second logic plane. The first logic plane receives a number of input signals. The
first logic plane has a plurality of logic cells arranged in rows and columns that
are interconnected to provide a number of logical outputs. The second logic plane
has a number of logic cells arranged in rows and columns that receive the outputs
of the first logic plane and that are interconnected to produce a number of logical
outputs such that the programmable logic array implements a logical function. Each
of the logic cells includes a vertical pillar extending outwardly from a semiconductor
substrate. Each pillar includes a single crystalline first contact layer and a
second contact layer separated by an oxide layer. Each logic cell further includes
at least one single crystalline ultra thin vertical transistor that is selectively
disposed adjacent the vertical pillar. The single crystalline vertical transistors
have an ultra thin single crystalline vertical first source/drain region coupled
to the first contact layer, an ultra thin single crystalline vertical second source/drain
region coupled to the second contact layer; and an ultra thin single crystalline
vertical body region which opposes the oxide layer and couples the first and the
second source/drain regions.
