The present invention provides a mechanism for supporting high bandwidth instruction
fetching in a multi-threaded processor. A multi-threaded processor includes an
instruction cache (I-cache) and a temporary instruction cache (TIC). In response
to an instruction pointer (IP) of a first thread hitting in the I-cache, a first
block of instructions for the thread is provided to an instruction buffer and a
second block of instructions for the thread are provided to the TIC. On a subsequent
clock interval, the second block of instructions is provided to the instruction
buffer, and first and second blocks of instructions from a second thread are loaded
into a second instruction buffer and the TIC, respectively.