Multi-tiered memory bank having different data buffer sizes with a programmable bank select

   
   

An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.

 
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< Data received before coherency window for a snoopy bus

< Computer system supporting both dirty-shared and non-dirty-shared data processing entities

> High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle

> Efficient method for mode change detection and synchronization

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