Disclosed is a method for converting a SPICE format circuit description
to a standard cell HDL netlist, such as Verilog, allowing simulation and verification
in HDL format. SPICE elements may be converted to circuit functions and corresponding
standard cells are then selected. The SPICE netlist is employed to define timing
paths. Timing information from SPICE simulation is correlated with timing characteristics
of the standard cells and a standard delay file is produced such that, when applied
to the standard cells, timing approximates that of the SPICE simulation. The present
invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is
converted to a Verilog standard cell netlist. Timing information from SPICE simulation
is correlated with timing characteristics of the standard cells in the Verilog
netlist and a standard delay file is produced such that, when applied to the standard
cells, timing approximates that of SPICE simulations.
