An electronic device may include a source memory device partitioned into N elementary
source memories for storing a sequence of input data sets, and a processor clocked
by a clock signal and having N outputs for producing, per cycle of the clock signal,
N output data sets respectively associated with the N input data sets stored in
the N elementary source memories at respective source addresses. The electronic
device may also include N single port target memories, N interleaving tables including,
for each relative source address, the number of a target memory and the respective
target address thereof, N cells connected in a ring structure. Further, each cell
may also be connected between an output of the processor, an interleaving table,
and a target memory.
