A microprocessor, data processing system, and method are disclosed for handling
parity errors in an address translation facility such as a TLB. The microprocessor
includes a load/store unit configured to generate an effective address associated
with a load/store instruction. An address translation unit adapted to translate
the effective address to a real address using a translation lookaside buffer (TLB).
The address translation unit includes a parity checker configured to verify the
parity of the real address generated by the TLB and to signal the load store unit
when the real address contains a parity error. The load store unit is configured
to initiate a TLB parity error interrupt routine in response to the signal from
the translation unit. In one embodiment, the TLB interrupt routine selectively
invalidates the TLB entry that contained the parity error. The load/store unit
preferably includes an effective to real address table (ERAT) containing a set
of address translations. In this embodiment, the load/store unit invokes the address
translation unit to translate the effective address only if the effective address
misses in the ERAT. The LSU may suitably include an ERAT miss queue (EMQ) adapted
to retain an effective address that misses in the ERAT until the address translation
unit completes the translation process. In this embodiment, the EMQ is configured
to issue a TLB parity error interrupt signal to initiate the TLB parity error interrupt
routine. In one embodiment, the TLB interrupt routine loads a data address register
(DAR) of the microprocessor with the effective address of the instruction that
resulted in the parity error. The TLB interrupt routine may further set a data
storage interrupt routine status register (DSISR) to indicate the TLB parity error.
