In a memory access process, by identifying the types of memories that can be
activated
without reducing operating speed and by reducing power consumption, a data processor
capable of operating at a high memory-accessing speed is provided. Because memory
types can often be differentiated based only on partial bits of the address obtained
by addition, a partial bit adder and decision logic are used to make this differentiation
at high speed. Because the partial addition preferably does not take into account
the possible carry from the lower bits, two types of memories are chosen from memories
and are both operated in case the carry should be "1" and in case it should be
"0." The result is chosen by a multiplexor and is output. A determination of the
entry address of the memory may be similarly carried out by dividing the memory
into odd and even entry number banks and utilizing a partial bit adder. Then, both
banks may be activated with the results of the partial bit adder as entries, and
one of the results is chosen for output.
