A method and apparatus is provided to debug using replicated logic. A text representation
of a circuit is compiled to generate a first register transfer level (RTL) netlist.
The netlist may be mapped to a target architecture, such as a field programmable
gate array (FPGA). The netlist may be used to program an FPGA to create a prototype
board for debugging. After debug, a portion of the circuit that a designer would
like to analyze is selected. The selected portion of the circuit is replicated.
Delay logic is inserted to delay the inputs into the replicated portion of the
circuit. The text representation of the circuit is recompiled to generate a second
RTL netlist. The second RTL netlist may be mapped to a target architecture, such
as a FPGA or application specific integrated circuit (ASIC).
