A sensing circuit including a sense amplifier to resolve a data signal generated
by a memory cell is disclosed herein. The sensing circuit includes a bit line to
receive the data signal, a first pre-charge device coupled to the bit line and
configured to pre-charge the bit line, a device for providing a bias coupled to
the bit line and configured to provide a bias to the bit line, and a reference
node configured to be at least one pre-determined level. In one embodiment the
pre-determined level is equal to a low potential such as ground and in another
embodiment equal to a high potential such as VDD. One or more switching
devices allows for the activation or deactivation of the pre-charge device allowing
to pre-charge the bit line to a certain potential and the sensing circuit quickly
and accurately determines whether a logical state of 1 or 0
is being applied to the bit line.
