An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed
for suitable use in high withstand voltage device applications, among others. The
LDMOS transistor includes a drain well region 21 formed in P-type substrate
1, and also formed therein spatially separated one another are a channel
well region 23 and a medium concentration drain region 24 having
an impurity concentration larger than that of drain well region 21, which
are simultaneously formed having a large diffusion depth through thermal processing.
A source 11s is formed in channel well region 23, while a
drain 11d is formed in drain region 24 having an impurity
concentration larger than that of drain region 24. In addition, a gate electrode
11g is formed over the well region, overlying the partially overlapped
portions with well region 23 and drain region 24 and being separated
from drain 11d. Since the source 11s, well region 23,
and drain region 24 are respectively self-aligned to the gate electrode
11g, resultant transistor characteristics are stabilized, and the
decrease in the on resistance and improved drain threshold voltages can be achieved.
Also disclosed herein are bipolar transistors with LDMOS structures, which are
capable of obviating the breakdown of gate dielectric layers even at high applied
voltage and achieving improved stability in transistor characteristics.
