An apparatus includes a first interface circuit, a second interface circuit, a
memory controller for configured to interface to a memory, and a packet DMA circuit.
The first interface circuit is configured to couple to a first interface for receiving
and transmitting packet data. Similarly, the second interface circuit is configured
to couple to a second interface for receiving and transmitting packet data. The
packet DMA circuit is coupled to receive a first packet from the first interface
circuit and a second packet from the second interface circuit. The packet DMA circuit
is configured to transmit the first packet and the second packet in write commands
to the memory controller to be written to the memory. In some embodiments, a switch
is coupled to the first interface circuit, the second interface circuit, and the
packet DMA circuit.
